Embedded Memory Design for Multi-Core and Systems on Chip, 1st Edition

  • Published By:
  • ISBN-10: 1461488818
  • ISBN-13: 9781461488811
  • DDC: 004.16
  • Grade Level Range: College Freshman - College Senior
  • 95 Pages | eBook
  • Original Copyright 2014 | Published/Released April 2014
  • This publication's content originally published in print form: 2014

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This book describes the various tradeoffs systems designers face when designing embedded memory. Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test. The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.

Table of Contents

Front Cover.
Other Frontmatter.
Title Page.
Copyright Page.
List of Figures.
List of Tables.
1: Introduction.
2: Cache Architecture and Main Blocks.
3: Embedded Memory Hierarchy.
4: SRAM-Based Memory Operation and Yield.
5: Power and Yield for SRAM Memory.
6: Leakage Reduction.
7: Embedded Memory Verification.
8: Embedded Memory Design Validation and Design for Test.
9: Emerging Memory Technology Opportunities and Challenges.