High-Bandwidth Memory Interface, 1st Edition

  • Published By:
  • ISBN-10: 3319023810
  • ISBN-13: 9783319023816
  • DDC: 621.397
  • Grade Level Range: College Freshman - College Senior
  • 88 Pages | eBook
  • Original Copyright 2014 | Published/Released April 2014
  • This publication's content originally published in print form: 2014

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This book provides an overview of recent advances in memory interface design at both the architecture and circuit levels. Coverage includes signal integrity and testing, TSV interface, high-speed serial interface including equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew cancellation, and clock generation and distribution. Trends for further bandwidth enhancement are also covered.

Table of Contents

Front Cover.
Other Frontmatter.
Title Page.
Copyright Page.
1: An Introduction to High-Speed DRAM.
2: An I/O Line Configuration and Organization of DRAM.
3: Clock Generation and Distribution.
4: Transceiver Design.
5: TSV Interface for DRAM.