High Performance Multi-Channel High-Speed I/O Circuits, 1st Edition

  • Published By:
  • ISBN-10: 1461449634
  • ISBN-13: 9781461449638
  • DDC: 621.38224
  • Grade Level Range: College Freshman - College Senior
  • 89 Pages | eBook
  • Original Copyright 2014 | Published/Released May 2014
  • This publication's content originally published in print form: 2014

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This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

Table of Contents

Front Cover.
Other Frontmatter.
Title Page.
Copyright Page.
1: Introduction.
2: 2 × 6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process.
3: 4 × 12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process.
4: Adaptive XTCR, AGC, and Adaptive DFE Loop.
5: Research Summary and Contributions.
Appendix A: Noise Analysis.
Appendix B: Issues of Applying Consecutive 2 × 2 XTCR on Multi-Lane I/Os (≥4).
Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter.
Appendix D: Line Mismatch Sensitivity.
Appendix E: Input Matching for 4 × 4 XTCR Receiver Test Bench.
Appendix F: Bandwidth Improvement by Technology Scaling.