Source-Synchronous Networks-On-Chip, 1st Edition

  • Published By:
  • ISBN-10: 1461494052
  • ISBN-13: 9781461494058
  • DDC: 621.381531
  • Grade Level Range: College Freshman - College Senior
  • 143 Pages | eBook
  • Original Copyright 2014 | Published/Released May 2014
  • This publication's content originally published in print form: 2014

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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Table of Contents

Front Cover.
Half Title Page.
Title Page.
Copyright Page.
1: Introduction.
2: Clock Distribution for Fast Networks-on-Chip.
3: Fast Network-on-Chip Design.
4: Fast On-Chip Data Transfer Using Sinusoid Signals.
5: Conclusion and Future Work.