Designing 2D and 3D Network-on-Chip Architectures, 1st Edition

  • Published By:
  • ISBN-10: 1461442745
  • ISBN-13: 9781461442745
  • DDC: 006.22
  • Grade Level Range: College Freshman - College Senior
  • 265 Pages | eBook
  • Original Copyright 2014 | Published/Released April 2014
  • This publication's content originally published in print form: 2014

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This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

Table of Contents

Front Cover.
Half Title Page.
Title Page.
Copyright Page.
1: Network-on-Chip Design Methodology.
2: Network-on-Chip Technology: A Paradigm Shift.
3: NoC Modeling and Topology Exploration.
4: Communication Architecture.
5: Power and Thermal Effects and Management.
6: NoC-Based System Integration.
7: NoC Verification and Testing.
8: The Spidergon STNoC.
9: Middleware Memory Management in NoC.
10: On Designing 3-D Platforms.
11: The SYSMANTIC NoC Design and Prototyping Framework.
12: Suggested Projects.
13: Projects on Network-on-Chip.