Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures, 1st Edition

  • Published By:
  • ISBN-10: 9400739583
  • ISBN-13: 9789400739581
  • DDC: 621.381531
  • Grade Level Range: College Freshman - College Senior
  • 174 Pages | eBook
  • Original Copyright 2013 | Published/Released May 2014
  • This publication's content originally published in print form: 2013

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Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

Table of Contents

Front Cover.
Other Frontmatter.
Title Page.
Copyright Page.
1: Introduction.
2: Literature Survey.
3: Motivational Example: MPEG-2 Encoder Design.
4: Target NoC Platform.
5: NoC Performance Analysis.
6: Application-Specific NoC Architecture Customization Using Long-Range Links.
7: Analysis and Optimization of Prediction-Based Flow Control in Networks-on-Chip.
8: Design and Management of VFI Partitioned Networks-on-Chip.
9: Conclusion.
Appendix A: Tools and FPGA Prototypes.
Appendix B: Experiments Using the Single-Chip Cloud Computer (SCC) Platform.