Higher Education

Chip Design for Submicron VLSI: CMOS Layout and Simulation, 1st Edition

  • John P. Uyemura Georgia Institute of Technology
  • ISBN-10: 053446629X  |  ISBN-13: 9780534466299
  • 411 Pages
  • © 2006 | Published
  • College Bookstore Wholesale Price = $163.50



The text is organized around first introducing the global view of digital integrated circuit design, VLSI and design automation, and then sequentially developing the topics from the materials and devices level, up through the circuits and then system level. This mirrors the structural hierarchy of the chip design field itself. While building a solid foundation and reference for the chip design, it integrates the discussion with hands-on examples of the design automation software, included in the book, to illustrate not only the layout and simulation concepts, but also how an industry designer would put them into practice. Both theory and application are effectively integrated into a cohesive treatment of the subject and art of chip design.

Features and Benefits

  • Contains a powerful CMOS layout program, Microwind. The code is fast and students can simulate a circuit using a BSIM4 MOSFET model. The 2-dimensional viewer displays the patterned layering along any selected line. The 3-dimensional simulator draws a 3D perspective view of the chip as it is fabricated.
  • Illustrates how material layers are patterned to create a CMOS integrated circuit in the first part of the book with Microwind. The discussion covers the basics of the CMOS fabrication sequence and how it relates to using a layout editor.
  • Covers the electrical characteristics of MOSFETs as they relate to the layout. Simple analytic expressions are compared to SPICE models in Microwind.
  • Provides CMOS logic circuits and chip design problems in the main portion of the book.
  • Includes a wealth of examples to help students master the material.
  • Students will have designed, and performed simulations and layouts of complete digital IC�s using a state of the art, portable, computer-aided design tool. This includes:·Integrated circuit layers, step by step examination of the CMOS fabrication sequence.·Hands-on chip design and layout without having prior CMOS physical design experience, including chip design considerations and limitations.·Hands-on experience using Microwind, an integrated chip layout and simulation automated design software package.

Table of Contents

Chapter 1. Installing the Microwind Software
1.1 Getting Started
1.2 Exploring Microwind
1.3 Installing Dsch
1.4 Plan of the Book
1.5 Some Important Details
1.6 References
Chapter 2. Views of a Chip
2.1 The Design Hierarchy
2.2 Integrated Circuit Layers
2.3 Photolithography and Patter Transfer
2.4 Planarization
2.5 Electrical Characteristics
2.6 Silicon Characteristics
2.7 Overview of Layout Design
2.8 References
2.9 Exercises
Chapter 3. CMOS Technology
3.1 Meet the MOSFETs
3.2 CMOS Fabrication
3.3 Submicron CMOS Processes
3.4 Process Technologies in Microwind
3.5 Masks and Layout
3.6 The Microwind MOS Generator
3.7 Chapter Summary and Roadmap
3.8 References
3.9 Exercises
Chapter 4. Using a Layout Editor
4.1 Lambda-Based Layout
4.2 Rectangles and Polygons
4.3 The MOS Generator Revisited
4.4 Summary
4.5 Exercises
Chapter 5. CMOS Design Rules
5.1 Types of Rules
5.2 The SCMOS Design Rule Set
5.3 FET Layout
5.4 References
5.5 Exercises
Chapter 6. MOSFETs
6.1 MOSFET Operation
6.2 MOSFET Switch Models
6.3 The Square Law Model
6.4 MOSFET Parasitics
6.5 Comments on Devise Layout
6.6 References
6.7 Exercises
Chapter 7. MOSFET Modeling with SPICE
7.1 SPICE Levels
7.2 MOSFET Modeling in Microwind
7.3 Circuit Extraction
7.4 Microwind Level 3 and BSIM4 Equations
7.5 References
7.6 Exercises
Chapter 8. CMOS Logic Gates
8.1 The Inverter
8.2 NAND and NOR Gates
8.3 Complex Logic Gates
8.4 The Microwind Compile Command
8.5 Tri-State Circuits
8.6 Large FETs
8.7 Transmission Gates and Pass Logic
8.8 References
8.9 Exercises
Chapter 9. Standard Cell Design
9.1 Cell Hierarchies
9.2 Cell Libraries
9.3 Library Entries
9.4 Cell Shapes and Floor Planning
9.5 References
9.6 Exercises
Chapter 10. Storage Elements
10.1 SR Latch
10.2 Bit-level Register
10.3 D-type Flip Flop
10.4 Dynamic DFF
10.5 The Static RAM Cell
10.6 References
10.7 Exercises
Chapter 11. Dynamic Logic Circuits
11.1 Basic Dynamic Logic Gates
11.2 Domino Logic
11.3 Self-Resetting Logic
11.4 Dynamic Memories
11.5 References
11.6 Exercises
Chapter 12. Interconnects
12.1 Modeling an Isolated Line
12.2 Long Interconnects
12.3 Crosstalk Capacitances
12.4 Interconnect Wiring Tools
12.5 General Routing Techniques
12.6 References
12.7 Exercises
Chapter 13. System Layout
13.1 Power Supply Distribution
13.2 Pad Generation
13.3 Input and Output Circuits
13.4 The Logo Generator
13.5 References
13.6 Exercises
Chapter 14. SOI Technology
14.1 Modern SOI CMOS
14.2 Why SOI?
14.3 Problems with SOI
14.4 SOI in Microwind
14.5 References
14.6 Exercises
Chapter 15. Digital System Design 1
15.1 A First Look
15.2 Editing Features
15.3 Creating a Logic Schematic
15.4 Simulating a Logic Design
15.5 Creating a Macro Symbol
15.6 Creating A Verilog ® Listing
15.7 The DSCH-Microwind Design Flow
15.8 Using a Design Toolset
15.9 MOSFETs in Dsch
15.10 References
15.11 Exercises
Chapter 16. Digital System Design 2
16.1 A 4-bit Binary Adder
16.2 Carry Lookahead Adder
16.3 Pipeline Register
16.4 Divide-by-N Circuit
16.5 Binary Counter
16.6 Summary
16.7 References
16.8 Exercises
Chapter 17. Capacitors and Inductors
17.1 Integrated Capacitors
17.2 Integrated Inductors
17.3 References
17.4 Exercises
Chapter 18. Analog CMOS Circuits
18.1 Simple Amplifiers
18.2 MOSFETs
18.3 Resistors
18.4 Signal Wiring
18.5 Summary
18.6 References
18.7 Exercises
Appendix 1. Microwind Command Summary
A.1 File
A.2 View
A.3 Edit
A.4 Simulate
A.5 Compile
A.6 Analysis
A.7 Help
A.8 Menu Bar
A.9 Other Screens
Appendix 2. Microwind CMOS Technology Files

Meet the Author

Author Bio

John P. Uyemura

John P. Uyemura is Professor of Electrical and Computer Engineering, late of Georgia Institute of Technology.